Bits left of bold letters are tag bits.Ġ0 0000 00 00 0000 0000 mandatory miss first time referencedĠ4 0000 00 00 0000 0100 Hit, since the index and tag is same as 0x00ġ0 0000 00 00 0001 0000 Hit, since the index and tag is same as 0x04Į8 0000 00 00 1110 1000 mandatory miss againĪ0 0000 00 00 1010 0000 mandatory miss againĤ00 0000 01 00 0000 0000 Miss, same index, different tag as 0x04ġE 0000 00 00 0001 1110 Miss, same index, different tag as 0x400ĨC 0000 00 00 1000 1100 Hit!! Same index as 4 th frameĬ1C 0000 11 00 0001 1100 Miss, same index, different tag as 0x1Eī4 0000 00 00 1011 0100 Hit!! Same index as 0xA0Ĩ84 0000 10 00 1000 0100 Miss since the frame needs replacementĥ.5) hit ratio is as simple as 4/12 or 0.33ĥ.6) To fill this table, I would suggest you to draw a cache on your note book and mark which blocks are being replace and are used. To check if it is a miss or a hit, we need to check its index values, so I have highlighted them. Therefore Total bits/Total data bits = (54+32*w)/(32*w).ĥ.4) Let us first convert each binary to their 16 bit binary form. So using those 5 bits we can uniquely identify 2 5 or 32 blocks in a directly mapped cache.ĥ.3) So if we consider very simple scenario with no dirty bit of valid bit for each line of the cache, we need 54 bits for tag field, and 32 words of suppose size w each. A cache is a smaller, faster memory, located closer to a processor core, which stores copies of the data from frequently used main memory locations. In this question we have bit 5-9 in the Index field. A CPU cache is a hardware cache used by the central processing unit (CPU) of a computer to reduce the average cost (time or energy) to access data from the main memory.

Index bits tell us how many blocks are present in a directly mapped cache. In this question we have 4 offset bits (0-4), therefore we have 2 5 or 32 words in a block (basic binary problem).ĥ.2) So the next obvious question would be what does then Index bits tell us. ĥ.1) We know that the block size can be determined by looking into the offset bits.

Tagĥ.1 What is the cache block size (in words)?ĥ.3 What is the ratio between total bits required for such a cache implementation over the data storage bits?īeginning from power on, the following byte-addressed cache references are recorded.ĥ.4 Foreachreference,list(1)itstag,index,ando set,(2)whether it is a hit or a miss, and (3) which bytes were replaced (if any).ĥ.6 List the final state of the cache,with each valid entry represented as a record of. For a direct-mapped cache design with a 64-bit address, the following bits of the address are used to access the cache.

Direct mapped cache tag index offset